1. Field of the Invention
The present invention relates to a semiconductor device having junction field effect transistors, and, more particularly, to a semiconductor device having junction field effect transistors, which can have the desired electric characteristics and do not affect other circuit elements on the same substrate.
2. Description of the Related Art
FIG. 1A is a plan view showing the structure of a conventional junction field effect transistor (FET), and FIG. 1B is a cross-sectional view along the line IB--IB in FIG. 1A. Hereinafter, this junction FET will be called "first prior art."
An N type epitaxial layer 22 having a thickness of approximately 3 .mu.m is grown on a P type semiconductor substrate 21. A P.sup.+ type insulative isolating layer 28 is selectively formed on the surface of the N type epitaxial layer 22 in such a way as to reach the P type semiconductor substrate 21. This insulative isolating layer 28 defines a device region 20 where a junction FET is to be formed.
An N.sup.+ type source diffusion layer 23, an N.sup.+ type drain diffusion layer 24 and a P.sup.+ type gate diffusion layer 25 are selectively formed on the N type epitaxial layer 22. An insulating film 36 is formed on the N type epitaxial layer 22 and the insulative isolating layer 28. A source contact hole 32, a drain contact hole 33 and a gate contact hole 34 are selectively formed in the insulating film 36 at the positions which match with the N.sup.+ type source diffusion layer 23, N.sup.+ type drain diffusion layer 24 and P.sup.+ type gate diffusion layer 25.
A source electrode 29, a drain electrode 30 and a gate electrode 31 are respectively formed on the N.sup.+ type source diffusion layer 23, N.sup.+ type drain diffusion layer 24 and P.sup.+ type gate diffusion layer 25 at those portions exposed by the contact holes 32, 33 and 34. Therefore, the source electrode 29, drain electrode 30 and gate electrode 31 are electrically connected to the N.sup.+ type source diffusion layer 23, N.sup.+ type drain diffusion layer 24 and P.sup.+ type gate diffusion layer 25 via the contact holes 32, 33 and 34 formed in the insulating film 36.
The distances from N.sup.+ type source diffusion layer 23 and N.sup.+ type drain diffusion layer 24 to the P.sup.+ type insulative isolating layer 28, P.sup.+ type gate diffusion layer 25 and P type semiconductor substrate 21 are so determined as to satisfy the breakdown voltage (e.g., 10 V) that is demanded of this junction FET.
In the thus constituted junction FET 20, when a DC voltage is applied to the source electrode 29 and drain electrode 30, a current flows between both electrodes 29 and 30 because those electrodes are electrically connected via the N type epitaxial layer 22. As the minus gate voltage is applied to the gate electrode 31 and P type semiconductor substrate 21, a depletion layer region 27a on the side of the gate electrode 31 and a depletion layer region 27b on the side of the P type semiconductor substrate 21 expand by the field effect. As a result, the width L of the N type channel region 26 becomes narrower, making it difficult for the current to flow. As is apparent from the above, the migration of electrons between the source electrode 29 and drain electrode 30 can be controlled by changing the level of the voltage to be applied to the gate electrode 31.
Therefore, the depth of the P.sup.+ type gate diffusion layer 25 formed between the N.sup.+ type source diffusion layer 23 and the N.sup.+ type drain diffusion layer 24 to isolate them from each other is an important factor for the performance of the junction FET 20. More specifically, as the P.sup.+ type gate diffusion layer 25 becomes deeper, the width L of the N type channel region 26 becomes narrower and the current I.sub.DSS that flows when a constant voltage is applied between the source electrode 29 and the drain electrode 30 becomes smaller. When the voltage to be applied to the source electrode 29 and the drain electrode 30 is constant, the gate voltage V.sub.GS necessary to turn off the junction FET becomes smaller.
The width L of the N type channel region 26 also varies greatly by a variation in the thickness of the epitaxial layer 22. Because the uniformness of the thickness of the epitaxial layer 22 is poor, the electric characteristics of the device are significantly influenced by a change in film thickness.
Therefore, the first prior art needs a step of checking the electric characteristics by a monitor device or the like during the fabrication of the junction FET and adjusting the depth of the gate diffusion layer 25 by a heat treatment or the like to provide the desired channel region width L.
The device manufacturing process suffers not only an increase in the number of steps but also the influence on the electric characteristics of other devices in the case of an LSI circuit on which those devices are simultaneously manufactured.
In an LSI circuit having NPN bipolar transistors or the like formed on the same substrate as this junction FET is formed, the impurity concentration of the P type silicon substrate 21 should be set as low as approximately 1.times.10.sup.15 cm.sup.-3 to reduce the collector capacitances of the NPN bipolar transistors. This scheme can improve the operation speed of the device and the collector breakdown voltage.
According to the junction FET of the first prior art, however, if the impurity concentration of the P type silicon substrate 21 is set low, it becomes difficult to increase the depletion layer region 27b to the desired range. This is because the impurity concentration of the P type silicon substrate 21 is lower than that of the N type epitaxial layer 22, so that the depletion layer formed by the PN junction between the P type silicon substrate 21 and the N type epitaxial layer 22 mainly expands toward the P type silicon substrate 21 and does not expand toward the N type epitaxial layer 22 much. Therefore, the mutual conductance (g.sub.m) representing the amount of a change in drain current (.DELTA.I.sub.DS) with respect to the amount of a change in gate voltage (.DELTA.V.sub.G) becomes smaller. In other words, even if the gate voltage to be applied is changed greatly, there is a small change in drain current so that the current control efficiency becomes poor.
As a junction FET with another structure, a junction FET with a vertical structure which has the source electrode and drain electrode formed on the top and back surfaces of a substrate is disclosed in, for example, Unexamined Japanese Patent Publication No. Sho 63-128769.
FIG. 2 is an exemplary cross-sectional view showing the structure of a junction FET with a vertical structure. This junction FET will be called "second prior art."
A drain region 42 made of an N type semiconductor is formed on the entire back surface of an N type semiconductor substrate 41, and a plurality of grooves 47 are formed inward from the surface of the N type semiconductor substrate 41 at the depth not deep enough to reach the drain region 42. A P type impurity is doped inside the N type semiconductor substrate 41 from all the grooves 47, forming P.sup.+ type gate diffusion layers 44 in such a way as to surround the grooves 47. N.sup.+ type source diffusion layers 43 are formed on the top surface of the N type semiconductor substrate 41 between the P.sup.+ type gate diffusion layers 44 in such a way as not to contact the individual P.sup.+ type gate diffusion layers 44.
An insulating film 48 is formed on the N type semiconductor substrate 41, and gate electrode holes 48a and source electrode holes 48b are respectively formed in the insulating film 48 at the positions matching with the openings 47a of the individual grooves 47 and the N.sup.+ type source diffusion layers 43.
Further, all the grooves 47 are filled with gate electrodes 46 which slightly protrude from the surface of the insulating film 48. Source electrodes 45 are formed on the source diffusion layers 43 which is exposed by the source electrode holes 48b. Like the gate electrodes 46, those source electrodes 45 slightly protrude from the surface of the insulating film 48. Therefore, the gate electrodes 46 are electrically connected to the P.sup.+ type gate diffusion layers 44, and the source electrodes 45 to the N.sup.+ type source diffusion layers 43.
The thus constituted junction FET has substantially the same operation as the first prior art except that the direction of the current flow differs from that of the first prior art. When a DC voltage is applied to the source electrodes 45 and the drain region 42, a current flows between the source electrodes 45 and the drain region 42 because they are electrically connected via the N type semiconductor substrate 41. As the minus gate voltage is applied to each gate electrode 46, the width of a channel region 49 between the adjoining gate electrodes 46 become narrower by the field effect, making it difficult for the current to flow.
In the junction FET of the second prior art, the migration of electrons between the source electrodes 45 and drain region 42 can likewise be controlled by changing the level of the voltage to be applied to the gate electrodes 46.
In the junction FET of the second prior art unlike the first prior art, the width of the channel region 49 between the adjoining gate electrodes 46 is not influenced by the film thickness of the N type semiconductor substrate 41, so that the electric characteristics can be improved.
As the drain region 42 is formed at the back of the N type semiconductor substrate 41 in the second prior art, however, the substrate potential varies when this junction FET is turned on or in an operation mode where a high current flows through the substrate 41. When circuit elements like NPN bipolar transistors besides the junction FET are formed on the same substrate, the NPN bipolar transistors or the like may malfunction.
Because the source diffusion layers 43 is formed between the adjacent gate diffusion layers 44 in the second prior art, this source diffusion layers 43 prevent the interval between the grooves 47 or the width of the channel region 49 from becoming narrower than a certain value, which is a design restriction. Further, when the depths of the grooves 47 become uneven, the lengths of the channel regions 49 in the depth direction of the grooves 47 also become uneven, thus causing a variation in the electric characteristics of the junction FET.